Cirkitly

yo Product Hunt 👋 i’m Utkarsh, an ECE student + builder of Spec2RTL (and a bunch more tools on the way 👀). i’ve spent way too many late nights writing Verilog from vague specs, debugging for hours, and wishing I had a smarter workflow. so I built Spec2RTL, an AI-powered copilot that takes you from spec to simulation in minutes. what it does: ⚡ takes a markdown spec ⚡ plans how to build the RTL + testbench ⚡ generates clean Verilog + SystemVerilog code ⚡ auto-validates with `iverilog` ⚡ critiques & fixes its own bugs ⚡ loops till the code is 💯 ⚡ and only then, asks for your approval supports Azure OpenAI and Ollama (yep, works locally too 🤘) it’s not just a codegen tool, it thinks, plans, reviews, and ships like a junior RTL engineer who doesn’t get tired if you're into hardware, EDA, AI, or just wanna spend less time debugging testbenches — check it out 🙌 and if you like it, a ⭐ means the world 👉 https://github.com/cirkitly/spec... PS: first 10 people to drop an idea in the issues tab might get their spec turned into a full RTL+TB module by Spec2RTL 😎